MT48LC32M16A2P-75:C

Product Overview

IC Picture

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Manufacturer Part No MT48LC32M16A2P-75:C
Brand MICRON
Item SDRAM
Part No 32MX16 SD
Alternate Names MT48LC32M16A2P-75 C
MT48LC32M16A2P-75:C MIC
MT48LC32M16A2P-75:C T/R
MT48LC32M16A2P-75:C TR MIC
MT48LC32M16A2P-75C
MT48LC32M16A2P75CTR

Product Details

Package TSOP2(54)
Outpack TRAY
RoHS RoHS
Voltage 3.3 V
Temperature 0 C~+70 C
Speed 133 MHZ
Std. Pack Qty 1000
Std. Carton
Number Of Words 32M
Bit Organization x16
Density 512M
Max Clock Frequency 133 MHz
Production Status Production
Package Material Pb-Free/RoHS-Plating
Product Family SDRAM/Mobile LPSDR
Version A2
Die Revision C

General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[12:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Available Offers

Description Qty Datecode
MT48LC32M16A2P-75:C T/R 30,197 1228 Get Quote
MT48LC32M16A2P-75C 33,724 10+ Get Quote
MT48LC32M16A2P-75C 30,047 13+ Get Quote
MT48LC32M16A2P-75C 40,000 15+ Get Quote
MT48LC32M16A2P-75C 33,951 Get Quote
MT48LC32M16A2P-75C 10,280 Get Quote
MT48LC32M16A2P-75C 2,800 11+ Get Quote
MT48LC32M16A2P-75C 3,886 15+ Get Quote
MT48LC32M16A2P-75C 8,212 10+ Get Quote
MT48LC32M16A2P-75C 7,000 15+ Get Quote

Cross Reference

Description Package Voltage Speed Temperature
AS4C32M16SB-7TCN TSOP2(54) 3.3 V 143 MHZ 0 C~+70 C
MT48LC32M16A2TG-75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2TG-75:C TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2TG-75:CTR TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2TG75TR TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
MT48LC32M16A2-75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2-75C TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A27G75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-7 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-75 TSOP2(54) 3.0V~3.6V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-75 L:C TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-75 OR K4S5 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
MT48LC32M16A2P-75: TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C