MT48LC4M32B2P-6:IT

Product Overview

IC Picture

Images are for reference only

Manufacturer Part No MT48LC4M32B2P-6:IT
Brand MICRON
Item SDRAM
Part No 4MX32 SD
Alternate Names MT48LC4M32B2P6IT

Product Details

Package TSOP2(86)
Outpack
RoHS RoHS
Voltage 3.3 V
Temperature -40 C~+85 C
Speed 166 MHZ
Std. Pack Qty
Std. Carton
Number Of Words 4M
Bit Organization x32
Density 128M
Max Clock Frequency 167 MHz
Production Status Production
Package Material Pb-Free/RoHS-Plating
Product Family SDRAM/Mobile LPSDR
Version B2
Die Revision I

General Description The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0–A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.

Available Offers

Description Qty Datecode
MT48LC4M32B2P6IT 0 Get Quote
MT48LC4M32B2P6IT 679 1004 Get Quote
MT48LC4M32B2P6IT 2,000 2012+ Get Quote
MT48LC4M32B2P6IT 100 6 Get Quote
MT48LC4M32B2P6IT 2,000 11+ Get Quote
MT48LC4M32B2P6IT 10,000 2012+ Get Quote
MT48LC4M32B2P6IT 100 06+ Get Quote
MT48LC4M32B2P6IT 2,000 Get Quote
MT48LC4M32B2P6IT 8,248 2012+ Get Quote
MT48LC4M32B2P6IT 2,000 2010+ Get Quote

Cross Reference

Description Package Voltage Speed Temperature
IS42S32400D-6TL TSOP2(86) 3.3 V 166 MHZ 0 C~+85 C

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
AS4C4M32S-6TIN TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
AS4C4M32SA-6TIN TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
AS4C4M32SA-6TINTR TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400B-6TI TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400B-6TLI TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400D-6TI TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400D-6TI-TR TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400D-6TLI TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400E-6TI-BM TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C
IS42S32400E-6TLI TSOP2(86) 3.3 V 166 MHZ -40 C~+85 C