MT48LC8M16A2P-75

Product Overview

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Manufacturer Part No MT48LC8M16A2P-75
Brand MICRON
Item SDRAM
Part No 8MX16 SD
Alternate Names MT48LC8M16A2P-75 (ROHS)
MT48LC8M16A2P-75 TR
MT48LC8M16A2P-75:

Product Details

Package TSOP2(54)
Outpack
RoHS RoHS
Voltage 3.3 V
Temperature 0 C~+70 C
Speed 133 MHZ
Std. Pack Qty
Std. Carton
Number Of Words 8M
Bit Organization x16
Density 128M
Max Clock Frequency 133 MHz
Production Status Production
Package Material Pb-Free/RoHS-Plating
Product Family SDRAM/Mobile LPSDR
Version A2

General Description The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

Available Offers

Description Qty Datecode
MT48LC8M16A2P-75 324 DC06 Get Quote
MT48LC8M16A2P-75 228 10+ Get Quote
MT48LC8M16A2P-75 67 Get Quote
MT48LC8M16A2P-75 6,000 16+ Get Quote
MT48LC8M16A2P-75 20,000 16+ Get Quote
MT48LC8M16A2P-75 2,000 2012+ Get Quote
MT48LC8M16A2P-75 3,300 2005+ Get Quote
MT48LC8M16A2P-75 3,000 2012+ Get Quote
MT48LC8M16A2P-75 1,000 09+ Get Quote
MT48LC8M16A2P-75 5,000 Get Quote

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
EDS1216AATA-75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75-E TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75-E TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75-F TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75E (LEADFREE TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75L-E TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA-75TH-E TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AATA75E128MTSOP TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AGTA-75 TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C
EDS1216AGTA-75-E TSOP2(54) 3.3 V 133 MHZ 0 C~+70 C