MT41J64M16JT-125:G

AB库存

产品概述

IC Picture

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制造商IC编号 MT41J64M16JT-125:G
厂牌 MICRON/美光
IC 类别 DDR3 SDRAM
IC代码 64MX16 DDR3
共通IC编号 MT41J64M16JT-125:GTR
MT41J64M16JT-125G

产品详情

脚位/封装 FBGA-96
外包装 TRAY
无铅/环保 无铅/环保
电压(伏) 1.5 V
温度规格 0 C~+95 C
速度 1600 MBPS
标准包装数量 1000
标准外箱
Number Of Words 64M
Bit Organization x16
Density 1G
Max Clock Frequency 800 MHz
Production Status Production
Product Family DDR3 SDRAM
Version J
Die Revision G

Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.

库存

IC 编号 数量 单价 (USD) 生产年份 附记
MT41J64M16JT-125:G 100 1308 AB库存 索取报价
MT41J64M16JT-125:G 100 1308 AB库存 索取报价

供应链有货

IC 编号 数量 生产年份
MT41J64M16JT-125G 166 索取报价
MT41J64M16JT-125G 4,277 155216+ 索取报价
MT41J64M16JT-125G 2,000 2016+ 索取报价
MT41J64M16JT-125G 2,675 索取报价
MT41J64M16JT-125G 2,667 索取报价
MT41J64M16JT-125G 2,000 索取报价
MT41J64M16JT-125:GTR 40,001 索取报价
MT41J64M16JT-125:GTR 20,001 索取报价
MT41J64M16JT-125:GTR 4,001 索取报价
MT41J64M16JT-125:GTR 2,001 索取报价

FFFE/互通料号 (形式,腳位和功能对等)

IC 编号 脚位/封装 电压(伏) 速度 温度规格
AS4C64M16D3-12BCN FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
AS4C64M16D3A-12BCN FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
AS4C64M16D3A-12BCNTR FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
AS4C64M16D3B-12BCN FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
AS4C64M16D3B-12BCNTR FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
H5TQ1G63AFR-PBC FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
H5TQ1G63BF-12C FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
H5TQ1G63BFR-12 FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
H5TQ1G63BFR-12C FBGA-96 1.5 V 1600 MBPS 0 C~+95 C
H5TQ1G63BFR-12C-C FBGA-96 1.5 V 1600 MBPS 0 C~+95 C