MT46V32M16CY-5BITJ

产品概述

IC Picture

图片仅供参考

制造商IC编号 MT46V32M16CY-5BITJ
厂牌 MICRON/美光
IC 类别 DDR1 SDRAM
IC代码 32MX16 DDR1
共通IC编号 MT46V32M16CY-5B IT:J
MT46V32M16CY-5B IT:J ROHS
MT46V32M16CY-5B IT:J TR

产品详情

脚位/封装 FBGA-60
外包装 TRAY
无铅/环保 无铅/环保
电压(伏) 2.5 V
温度规格 -40 C~+85 C
速度 200 MHZ
标准包装数量 1368
标准外箱
Number Of Words 32M
Bit Organization x16
Density 512M
Max Clock Frequency 200 MHz
Production Status Production
Product Family DDR SDRAM/Mobile LPDDR
Version C
Die Revision J

Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible.

供应链有货

IC 编号 数量 生产年份
MT46V32M16CY-5BITJ 6,000 2022+ 索取报价
MT46V32M16CY-5BITJ 2,000 索取报价
MT46V32M16CY-5B IT:J TR 8,000 索取报价
MT46V32M16CY-5BITJ 1,368 索取报价
MT46V32M16CY-5BITJ 2,000 22+ 索取报价
MT46V32M16CY-5B IT:J 1,000 索取报价
MT46V32M16CY-5B IT:J 1,311 索取报价
MT46V32M16CY-5B IT:J 100,000 索取报价
MT46V32M16CY-5B IT:J 50,000 索取报价
MT46V32M16CY-5B IT:J 20,000 索取报价

FFFE/互通料号 (形式,腳位和功能对等)

IC 编号 脚位/封装 电压(伏) 速度 温度规格
IS43R16320D -5BLA1 BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320D-5BLI BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320E -5BLA1 BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320E-5BI FBGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320E-5BLI BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320F -5BLA1 BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS43R16320F-5BLI BGA-60 2.5 V 200 MHZ -40 C~+85 C
IS46R16320D-5BLA1 FBGA-60 2.5 V 200 MHZ -40 C~+85 C
IS46R16320D-5BLA1-BM FBGA-60 2.5 V 200 MHZ -40 C~+85 C
IS46R16320D-5BLA1-TR FBGA-60 2.5 V 200 MHZ -40 C~+85 C