K5N3217ATA-AT8T0TN

GENERAL DESCRIPTION The K5N3217ATA is a MultiChip Package Memory which combines 32Mbit MuxNOR Flash Memory and 16M bit MuxUtRAM2. The 32Mb NOR Flash featuring single 1.8V power supply is 32Mbit Synchronous Burst Multi B ank Flash Memory organized as 2Mx16. T he memory architecture of the device is designed to dividememory arrays into 71 blocks wi th independent hardware protection. This block architecture provides highly flexible erase and program capability. The 32Mb NOR Flas h consists of sixteen banks. This device i s capable of reading data from one bank while programming or erasing in the other bank. Regar ding read access time, the device provides an 1 4.5ns burst access time and an 70ns initial access time at 54MHz. At 66MHz, the device provides an 11ns burst access time and 70ns initial access time. At 83MHz, the device provides an 9ns burst access time and 70ns initial acctime. At 108MHz, the device provides an 7n s burst access time and 70ns initial access time. The device performs a program operation in units of 16bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7sec. The device requires 15mA as program/erase current in the extended temperature ranges. SAMSUNG’s UtRAM products are designed to meet the request from the customers who want to cope with the fast growing mobile applica- tions that need high-speed random access memory. UtRAM is the solution for the mobile market with its low cost, high density and high per- formance feature. device is fabricated by SAMSUNG′s advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous operation (asynchronous read and asynchronous write), the NOR flash like synchronous operation (synchronous burst read and asynchronous write) and the fully syronous operation (synchronous burst read and synchronous bur st write). These operation modes are defined through the configuratio n register setting. It supports the special features for the standby power saving. Those are the PAR(Partial Array Refresh) mode, DPD(DeepPower Down) mode and internal TCSR(Temperature Compensated Self Refresh). It also supports variable and fixed latency, driver strength settings, Burst sequence (wrap or No-wrap) options and a device ID register (DIDR). The K5N3217ATA is suitable for use in data memory of mobile co mmunication system to reduce not only mount area but also power c on- sumption. This device is available in 52-ball FBGA Type.