| 脚位/封装 |
FBGA-54
|
| 外包裝 |
|
| 無鉛/環保 |
無鉛/環保
|
| 電壓(伏) |
1.8 V
|
| 溫度規格 |
-40 C~+85 C
|
| 速度 |
133 MHZ
|
| 標準包裝數量 |
|
| 標準外箱 |
|
General Description
The Micron® 64Mb SDRAM is a high-speed CMOS, dynamic random access memory
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns
by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations with a burst terminate option. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at the end of the burst sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also
enables the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the PRECHARGE cycles and provide seamless high-speed, random-access
operation.
The 64Mb SDRAM is designed to operate in 1.8V, low-power memory systems. An auto
refresh mode is provided, along with a power-saving, deep power-down mode. All inputs
and outputs are LVTTL-compatible.
