MT48LC32M16A2P-75IT:C

產品概述

IC Picture

圖片僅供參考

製造商IC編號 MT48LC32M16A2P-75IT:C
廠牌 MICRON/美光
IC 類別 SDRAM
IC代碼 32MX16 SD
共通IC編號 MT48LC32M16A2P-75 IT:C
MT48LC32M16A2P-75 IT:C MIC
MT48LC32M16A2P-75 IT:C TR
MT48LC32M16A2P-75:IT:C
MT48LC32M16A2P-75ITC
MT48LC32M16A2P-75ITCTR

產品詳情

脚位/封装 TSOP2(54)
外包裝
無鉛/環保 無鉛/環保
電壓(伏) 3.3 V
溫度規格 -40 C~+85 C
速度 133 MHZ
標準包裝數量
標準外箱
Number Of Words 32M
Bit Organization x16
Density 512M
Max Clock Frequency 133 MHz
Production Status Production
Package Material Pb-Free/RoHS-Plating
Product Family SDRAM/Mobile LPSDR
Version A2
Die Revision C

General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[12:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

供應鏈有貨

IC 編號 數量 生產年份
MT48LC32M16A2P-75ITC 681 索取報價
MT48LC32M16A2P-75ITC 150 索取報價
MT48LC32M16A2P-75ITC 1,823 1422+ 索取報價
MT48LC32M16A2P-75ITC 325 184813+ 索取報價
MT48LC32M16A2P-75ITC 424 索取報價
MT48LC32M16A2P-75ITC 1,000 D/C 14+ 索取報價
MT48LC32M16A2P-75ITC 2,000 索取報價
MT48LC32M16A2P-75ITC 1,000 索取報價
MT48LC32M16A2P-75ITC 88 2008+ 索取報價
MT48LC32M16A2P-75ITC 188 2008+ 索取報價

FFFE/互通料號 (形式,腳位和功能對等)

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
IS42S16320B-75ETLI TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
IS42S16320B675ETLI TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632B-TI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632C-TI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632D-TI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632D-UI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632D-UI75T TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632K-UI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632K-UI75T TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C
K4S511632M-TI75 TSOP2(54) 3.3 V 133 MHZ -40 C~+85 C