MT48LC8M16A2P-6AIT:L

產品概述

IC Picture

圖片僅供參考

製造商IC編號 MT48LC8M16A2P-6AIT:L
廠牌 MICRON/美光
IC 類別 SDRAM
IC代碼 8MX16 SD
共通IC編號 MT48LC8M16A2P-6A IT:L
MT48LC8M16A2P-6A IT:L TR
MT48LC8M16A2P-6AITLTR
MT48LC8M16A2P6AITL

產品詳情

脚位/封装 TSOP2(54)
外包裝 TRAY
無鉛/環保 無鉛/環保
電壓(伏) 3.3 V
溫度規格 -40 C~+95 C
速度 167 MHZ
標準包裝數量 1080
標準外箱
Number Of Words 8M
Bit Organization x16
Density 128M
Max Clock Frequency 167 MHz
Production Status Production
Package Material Pb-Free/RoHS-Plating
Product Family SDRAM/Mobile LPSDR
Version A2
Die Revision L

General Description The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

供應鏈有貨

IC 編號 數量 生產年份
MT48LC8M16A2P-6AIT:L 5,000 2022 索取報價
MT48LC8M16A2P-6AIT:L 421 索取報價
MT48LC8M16A2P-6AIT:L 2,000 2023+ 索取報價
MT48LC8M16A2P-6AIT:L 10,000 23+ 索取報價
MT48LC8M16A2P-6AIT:L 8,954 索取報價
MT48LC8M16A2P-6A IT:L TR 4,000 索取報價
MT48LC8M16A2P-6A IT:L TR 1,517 索取報價
MT48LC8M16A2P-6AIT:L 0 索取報價
MT48LC8M16A2P-6AIT:L 16,000 索取報價
MT48LC8M16A2P-6AIT:L 2,000 23+ 索取報價

可替代IC編號

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
W9812G6KH-6-TR TSOP2(54) 3.3 V 166 MHZ 0 C~+70 C

FFFE/互通料號 (形式,腳位和功能對等)

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
MT48LC8M16A2P-6A AIT:L TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6A AIT:L TR TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6A IT:G TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6A IT:J TR TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6AAIT TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6AIT TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P-6AITG TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2P6AAITL TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2TG-6A AIT:L TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C
MT48LC8M16A2TG-6A IT:G TSOP2(54) 3.3 V 167 MHZ -40 C~+95 C