MT48H32M16LFB4-75ITC

General Description The 512Mb Mobile LPSDR is a high-speed CMOS, dynamic random-access memory containing 536,870,912-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1K columns by 16 bits. Each of the x32’s 134,217,728-bit banks is organized as 8192 rows by 512 columns by 32 bits. In the reduced page size option, each of the x32’s 134,217,728-bit banks is organized as 16,384 rows by 256 columns by 32 bits. Mobile LPSDR offers substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Note: 1. Throughout the data sheet, various figures and text refer to DQs as DQ. DQ should be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes: the lower byte and the upper byte. For the lower byte (DQ[7:0]), DQM refers to LDQM. For the upper byte (DQ[15:8]), DQM refers to UDQM. The x32 is divided into four bytes. For DQ[7:0], DQM refers to DQM0. For DQ[15:8], DQM refers to DQM1. For DQ[23:16], DQM refers to DQM2, and for DQ[31:24], DQM refers to DQM3. 2. Complete functionality is described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. Any specific requirement takes precedence over a general statement.