MT48V16M32L2B5-8

General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured by stacking two 256Mb, 8 Meg x 32 devices. Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous interface. They are organized with 32 DQs with 4 banks of 67,108,864 bits, comprising of 8,192 rows by 512 columns by 32 bits wide. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V, 2.5V, and 1.8V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering die intitialization, register definition, command descriptions, and device operation on a per die basis unless otherwise noted. This addendum documents any variances for the 512Mb: x32 Mobile SDRAM from the 256Mb: x32 Mobile SDRAM specification. Please refer to the 256Mb: x32 Mobile SDRAM data sheet on Micron’s Web site for additional details on the part functionality.