MT44K32M18RB-125:A

General Description The MicronŠ RLDRAMŠ 3 is a high-speed memory device designed for high-bandwidth data storage—telecommunications, networking, cache applications, etc. The chip’s 16bank architecture is optimized for sustainable high-speed operation. The DDR I/O interface transfers two data bits per clock cycle at the I/O balls. Output data is referenced to the READ strobes. Commands, addresses, and control signals are also registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data strobes. Read and write accesses to the RL3 device are burst-oriented. The burst length (BL) is programmable to 2, 4, or 8 by a setting in the mode register. The device is supplied with 1.35V for the core and 1.2V for the output drivers. The 2.5V supply is used for an internal supply. Bank-scheduled refresh is supported with the row address generated internally. The 168-ball FBGA package is used to enable ultra-high-speed data transfer rates.

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