| 脚位/封装 |
FBGA-48
|
| 外包装 |
TAPE ON REEL
|
| 无铅/环保 |
无铅/环保
|
| 电压(伏) |
1.8 V
|
| 温度规格 |
-35 C~+85 C
|
| 速度 |
70 NS
|
| 标准包装数量 |
|
| 标准外箱 |
|
General Description
Micron® CellularRAM™ products are high-speed, CMOS PSRAM memories developed
for low-power, portable applications. The MT45W2MW16P is a 32Mb DRAM core device
organized as 2 Meg x 16 bits. These devices include the industry-standard, asynchronous
memory interface found on other low-power SRAM or pseudo-SRAM offerings.
A user-accessible configuration register (CR) defines how the CellularRAM device
performs on-chip refresh and whether page mode read accesses are permitted. This
register is automatically loaded with a default setting during power-up and can be
updated at any time during normal operation.
For seamless operation on an asynchronous memory bus, CellularRAM products incorporate a transparent self-refresh mechanism. The hidden refresh requires no additional
support from the system memory controller and has no significant impact on device
read/write performance.
Special attention has been focused on current consumption during self refresh. CellularRAM products include three system-accessible mechanisms to minimize refresh
current. Temperature-compensated refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The refresh rate decreases at lower
temperatures to minimize current consumption during standby. Setting sleep enable
(ZZ#) to LOW enables one of two low-power modes: partial-array refresh (PAR) or deep
power-down (DPD). PAR limits refresh to only that part of the DRAM array that contains
essential data. DPD halts refresh operation altogether and is used when no vital information is stored in the device. The system-configurable refresh mechanisms are
accessed through the CR.
