| 脚位/封装 |
TSOP-66
|
| 外包装 |
|
| 无铅/环保 |
含铅
|
| 电压(伏) |
2.5 V
|
| 温度规格 |
0 C~+85 C
|
| 速度 |
133 MHZ
|
| 标准包装数量 |
|
| 标准外箱 |
|
| Number Of Words |
8M
|
| Bit Organization |
x16
|
| Density |
128M
|
| Max Clock Frequency |
133 MHz
|
| Production Status |
Production
|
| Product Family |
DDR SDRAM/Mobile LPDDR
|
| Version |
T
|
| Die Revision |
B
|
DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
134,217,728 bits. The 128Mb DDR SDRAM is internally
configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture, with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the 128Mb DDR SDRAM consists of
a single 2n-bit wide, one-clock-cycle data transfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE
command are used to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must
be initialized. The following sections provide detailed
information covering device initialization, register definition, command descriptions and device operation.
