NAND256W3A-2BN6

Description The NAND flash 528 byte/ 264 word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND cell technology, referred to as the SLC small page family. The devices are either 128 Mbits or 256 Mbits and operate with a 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width. The address lines are multiplexed with the data input/output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. Each block can be programmed and erased up to 100,000 cycles. To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). A Write Protect pin is available to provide hardware protection against program and erase operations. The devices feature an open-drain ready/busy output that identifies if the program/erase/ read (P/E/R) controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Copy Back command is available to optimize the management of defective blocks. When a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. Table 1 lists the individual part numbers of the device. Table 1.