H27U2G8F2CTR-BC

產品概述

IC Picture

圖片僅供參考

製造商IC編號 H27U2G8F2CTR-BC
廠牌 SK HYNIX/海力士
IC 類別 FLASH-NAND
IC代碼 256MX8 NAND SLC

產品詳情

脚位/封装 TSOP-48
外包裝 TAPE ON REEL
無鉛/環保 無鉛/環保
電壓(伏) 2.7V-3.6V
溫度規格 0 C~+70 C
速度 25 NS
標準包裝數量 2000
標準外箱

Description...................................................................................................................5 1.1 Product List....................................................................................................................................6 1.2 Pin description................................................................................................................................9 1.3 Functional block diagram...............................................................................................................10 1.4 Address role.................................................................................................................................11 1.5 Command Set...............................................................................................................................12 2 Bus Operations............................................................................................................................14 2.1 Command Input............................................................................................................................14 2.2 Address Input...............................................................................................................................14 2.3 Data Input....................................................................................................................................14 2.4 Data Output.................................................................................................................................14 2.5 Write Protect................................................................................................................................14 2.6 Stand-by......................................................................................................................................14 3 DEVICE OPERATION...................................................................................................................15 3.1 Page Read....................................................................................................................................15 3.2 Data Handiling Restriction During Program Sequences......................................................................15 3.3 Page Program...............................................................................................................................15 3.4 Multiple plane program..................................................................................................................16 3.5 Block Erase...................................................................................................................................16 3.6 Multiple plane Block Erase..............................................................................................................17 3.7 Copy-Back Program.......................................................................................................................17 3.8 Multiple plane copy back Program...................................................................................................18 3.9 Special read for copy back..............................................................................................................18 3.10 EDC Operation............................................................................................................................18 3.11 Read Status Register...................................................................................................................20 3.12 Read Status Enhanced.................................................................................................................20 3.13 Read Status Register field definition..............................................................................................21 3.14 Read EDC Status Register............................................................................................................21 3.15 Reset.........................................................................................................................................22 3.16 Cache Read................................................................................................................................22 3.17 Cache Program...........................................................................................................................23 3.18 Multi-plane Cache Program..........................................................................................................23 3.19 Read ID......................................................................................................................................25 3.19.1 Legacy Read ID........................................................................................................................25 3.20 Read ONFI Signature...................................................................................................................27 3.21 Read Parameter Page..................................................................................................................27 3.22 Parameter Page Data Structure Definition......................................................................................27 4 OTHER FEATURES.......................................................................................................................30 4.1 Data Protection and Power on / off sequence...................................................................................30 4.2 Ready/Busy..................................................................................................................................30 4.3 Write protect (#WP) handling........................................................................................................30 5 Device Parameters......................................................................................................................31 6 Timing Diagrams.........................................................................................................................35 7 Package Mechanical....................................................................................................................58 7.1 Power consumptions and pin capacitance for allowed stacking configurations.....................................60 8 Application notes and comments...............................................................................................61 8.1 System Interface using CE# don't care............................................................................................61 8.2 System Bad Block Replacement......................................................................................................62 8.3 Bad Block Management.................................................................................................................

供應鏈有貨

IC 編號 數量 生產年份
H27U2G8F2CTR-BC 0 索取報價
H27U2G8F2CTR-BC 5,760 索取報價
H27U2G8F2CTR-BC 5,760 18+ 索取報價
H27U2G8F2CTR-BC 3,840 18+ 索取報價
H27U2G8F2CTR-BC 1,920 18+ 索取報價
H27U2G8F2CTR-BC 1,920 索取報價
H27U2G8F2CTR-BC 1,000 2 索取報價
H27U2G8F2CTR-BC 7,445 0 索取報價
H27U2G8F2CTR-BC 152 1327+ 索取報價
H27U2G8F2CTR-BC 3,840 索取報價

可替代IC編號

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
HY27UF082G2B-TPCB TSOP 2.7V~3.6V 0 C~+70 C

FFFE/互通料號 (形式,腳位和功能對等)

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
H27U2G8CTR-BCR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2BTR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2C TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2CFR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2CTR-BCR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2DTR-B TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2DTR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8F2DTR-BCR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8FCTR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U2G8FDTR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C