H27U4G8F2DTR-BC

產品概述

IC Picture

圖片僅供參考

製造商IC編號 H27U4G8F2DTR-BC
廠牌 SK HYNIX/海力士
IC 類別 FLASH-NAND
IC代碼 512MX8 NAND SLC

產品詳情

脚位/封装 TSOP-48
外包裝 TRAY
無鉛/環保 無鉛/環保
電壓(伏) 2.7V-3.6V
溫度規格 0 C~+70 C
速度 25 NS
標準包裝數量 960
標準外箱

Description...................................................................................................................5 1.1 Product List....................................................................................................................................6 1.2 Pin description................................................................................................................................8 1.3 Functional block diagram...............................................................................................................9 1.4 Address role.................................................................................................................................10 1.5 Command Set...............................................................................................................................11 2 Bus Operations............................................................................................................................13 2.1 Command Input............................................................................................................................13 2.2 Address Input...............................................................................................................................13 2.3 Data Input....................................................................................................................................13 2.4 Data Output.................................................................................................................................13 2.5 Write Protect................................................................................................................................13 2.6 Stand-by......................................................................................................................................13 3 DEVICE OPERATION...................................................................................................................14 3.1 Page Read....................................................................................................................................14 3.2 Data Handiling Restriction During Program Sequences......................................................................14 3.3 Page Program...............................................................................................................................14 3.4 Multiple plane program..................................................................................................................15 3.5 Block Erase...................................................................................................................................15 3.6 Multiple plane Block Erase..............................................................................................................16 3.7 Copy-Back Program.......................................................................................................................16 3.8 Multiple plane copy back Program...................................................................................................17 3.9 Special read for copy back..............................................................................................................17 3.10 EDC Operation........................................................................................................................17 3.11 Read Status Register...................................................................................................................19 3.12 Read Status Enhanced.................................................................................................................19 3.13 Read Status Register field definition..............................................................................................20 3.14 Read EDC Status Register............................................................................................................20 3.15 Reset.........................................................................................................................................21 3.16 Cache Read................................................................................................................................21 3.17 Cache Program...........................................................................................................................22 3.18 Multi-plane Cache Program..........................................................................................................22 3.19 Read ID......................................................................................................................................24 3.20 Read ONFI Signature...................................................................................................................26 3.21 Read Parameter Page..................................................................................................................26 3.22 Parameter Page Data Structure Definition......................................................................................26 4 OTHER FEATURES.......................................................................................................................30 4.1 Data Protection and Power on / off sequence...................................................................................30 4.2 Ready/Busy..................................................................................................................................30 4.3 Write protect (#WP) handling........................................................................................................30 5 Device Parameters......................................................................................................................31 6 Timing Diagrams.........................................................................................................................35 7 Package Mechanical...............................................................................................................58 7.1 Power consumptions and pin capacitance for allowed stacking configurations.....................................59 8 Application notes and comments.............................................................................................60 8.1 System Interface using CE# don't care..........................................................................................60 8.2 System Bad Block Replacement....................................................................................................61 8.3 Bad Block Management System....................................................................................................

供應鏈有貨

IC 編號 數量 生產年份
H27U4G8F2DTR-BC 10 201929 索取報價
H27U4G8F2DTR-BC 252 索取報價
H27U4G8F2DTR-BC 5,760 索取報價
H27U4G8F2DTR-BC 3,840 索取報價
H27U4G8F2DTR-BC 10 21+ 索取報價
H27U4G8F2DTR-BC 29 NA 索取報價
H27U4G8F2DTR-BC 4,800 索取報價
H27U4G8F2DTR-BC 19,200 索取報價
H27U4G8F2DTR-BC 1,920 索取報價
H27U4G8F2DTR-BC 38 索取報價

FFFE/互通料號 (形式,腳位和功能對等)

IC 編號 脚位/封装 電壓(伏) 速度 溫度規格
H27U4G8F2BTR/BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2CTR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2D TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DFR-BC TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR T R TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR-BC 3441PCS TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR-BCDR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR-BCR TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C
H27U4G8F2DTR-BCUSD TSOP-48 2.7V-3.6V 25 NS 0 C~+70 C