圖片僅供參考
製造商IC編號 | H27U4G8F2DTR-BCDR |
廠牌 | SK HYNIX/海力士 |
IC 類別 | FLASH-NAND |
IC代碼 | 512MX8 NAND SLC |
脚位/封装 | TSOP-48 |
外包裝 | |
無鉛/環保 | 無鉛/環保 |
電壓(伏) | 2.7V-3.6V |
溫度規格 | 0 C~+70 C |
速度 | 25 NS |
標準包裝數量 | |
標準外箱 |
Description...................................................................................................................5 1.1 Product List....................................................................................................................................6 1.2 Pin description................................................................................................................................8 1.3 Functional block diagram...............................................................................................................9 1.4 Address role.................................................................................................................................10 1.5 Command Set...............................................................................................................................11 2 Bus Operations............................................................................................................................13 2.1 Command Input............................................................................................................................13 2.2 Address Input...............................................................................................................................13 2.3 Data Input....................................................................................................................................13 2.4 Data Output.................................................................................................................................13 2.5 Write Protect................................................................................................................................13 2.6 Stand-by......................................................................................................................................13 3 DEVICE OPERATION...................................................................................................................14 3.1 Page Read....................................................................................................................................14 3.2 Data Handiling Restriction During Program Sequences......................................................................14 3.3 Page Program...............................................................................................................................14 3.4 Multiple plane program..................................................................................................................15 3.5 Block Erase...................................................................................................................................15 3.6 Multiple plane Block Erase..............................................................................................................16 3.7 Copy-Back Program.......................................................................................................................16 3.8 Multiple plane copy back Program...................................................................................................17 3.9 Special read for copy back..............................................................................................................17 3.10 EDC Operation........................................................................................................................17 3.11 Read Status Register...................................................................................................................19 3.12 Read Status Enhanced.................................................................................................................19 3.13 Read Status Register field definition..............................................................................................20 3.14 Read EDC Status Register............................................................................................................20 3.15 Reset.........................................................................................................................................21 3.16 Cache Read................................................................................................................................21 3.17 Cache Program...........................................................................................................................22 3.18 Multi-plane Cache Program..........................................................................................................22 3.19 Read ID......................................................................................................................................24 3.20 Read ONFI Signature...................................................................................................................26 3.21 Read Parameter Page..................................................................................................................26 3.22 Parameter Page Data Structure Definition......................................................................................26 4 OTHER FEATURES.......................................................................................................................30 4.1 Data Protection and Power on / off sequence...................................................................................30 4.2 Ready/Busy..................................................................................................................................30 4.3 Write protect (#WP) handling........................................................................................................30 5 Device Parameters......................................................................................................................31 6 Timing Diagrams.........................................................................................................................35 7 Package Mechanical...............................................................................................................58 7.1 Power consumptions and pin capacitance for allowed stacking configurations.....................................59 8 Application notes and comments.............................................................................................60 8.1 System Interface using CE# don't care..........................................................................................60 8.2 System Bad Block Replacement....................................................................................................61 8.3 Bad Block Management System....................................................................................................
IC 編號 | 脚位/封装 | 電壓(伏) | 速度 | 溫度規格 |
---|---|---|---|---|
K9F4G08U0A-PCB00T00 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A-PCB0T00 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A-PCBT | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A-YCB0 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A-YCBO | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A/B-PCB0 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0A/M-PCB0 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0AM-PCB | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0APCB | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |
K9F4G08U0APCB00 | TSOP-48 | 2.7V-3.6V | 25 NS | 0 C~+70 C |