| 脚位/封装 |
TSOP-48
|
| 外包裝 |
TAPE ON REEL
|
| 無鉛/環保 |
無鉛/環保
|
| 電壓(伏) |
3.3 V
|
| 溫度規格 |
-40 C~+105 C
|
| 速度 |
25 NS
|
| 標準包裝數量 |
1000
|
| 標準外箱 |
|
| Number Of Words |
512M
|
| Bit Organization |
x8
|
| Density |
4G
|
| Production Status |
Production
|
| Package Material |
Pb-free
|
| Interface |
Async only
|
| Level |
SLC
|
| Generation Feature Set |
4th set of device features (rev only if different)
|
| Speed Grade |
Async only
|
| Design Revision |
D
|
| Features |
Product Longevity Program
|
| Package |
TSOP I(48-pin CPL version)
|
| Classification |
1-1-1-1 (Die-nCE-RnB-IO Channels)
|
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
