MT41J256M8DA-107 ES:M

產品概述

IC Picture

圖片僅供參考

製造商IC編號 MT41J256M8DA-107 ES:M
廠牌 MICRON/美光
IC 類別 DDR3 SDRAM
IC代碼 256MX8 DDR3

產品詳情

脚位/封装 FBGA-78
外包裝
無鉛/環保 無鉛/環保
電壓(伏) 1.5 V
溫度規格 0 C~+85 C
速度 1866 MBPS
標準包裝數量
標準外箱
Number Of Words 256M
Bit Organization x8
Density 2G
Max Clock Frequency 933 MHz
Production Status Production
Product Family DDR3 SDRAM
Version D

Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.

供應鏈有貨

IC 編號 數量 生產年份
MT41J256M8DA-107 ES:M 0 索取報價
MT41J256M8DA-107 ES:M 6,000 索取報價

FFFE/互通料號 (形式,腳位和功能對等)

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H5TQ2G83FFR-RDA FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
H5TQ2G83GFR-RDA FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
H5TQ2G83GFR-RDC D3 256X FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
H5TQ2G83GFR-RDCR FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
IS43TR82560B-107MBL FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
IS43TR82560B-107MBL-TR FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
IS43TR82560B-107MBLC FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
IS43TR82560C-107MBL FBGA-78 1.5 V 1866 MBPS 0 C~+85 C
IS43TR82560C-107MBL-TR FBGA-78 1.5 V 1866 MBPS 0 C~+85 C