MT4C1M16C3TG-5S
產品詳情
| 脚位/封装 | TSOP2(44/50) |
| 外包裝 | |
| 無鉛/環保 | 含鉛 |
| 電壓(伏) | 5.0 V |
| 溫度規格 | 0 C~+70 C |
| 速度 | 50 NS |
| 標準包裝數量 | |
| 標準外箱 |
GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
供應鏈有貨
| IC 編號 | 數量 | 生產年份 | |
|---|---|---|---|
| MT4C1M16C3TG-5S | 30,000 | 2008+ | 索取報價 |
FFFE/互通料號 (形式，腳位和功能對等)
| IC 編號 | 脚位/封装 | 電壓(伏) | 速度 | 溫度規格 |
|---|---|---|---|---|
| AS4C1M16F5-50TC | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C16160BT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C16160CT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C18160CT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C18160CT-50 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5116160LTT5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5118160LTT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5118160TT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| MT4C1M16C3TG-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| MT4C1M16C3TG-5T | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |