MT4LC1M16C3TG-5L
Produktbeschreibung
| Gehäuse | TSOP2(44/50) |
| Verpackung | |
| RoHS | Leaded |
| Spannungsversorgung | 3.3 V |
| Betriebstemperatur | 0 C~+70 C |
| Geschwindigkeit | 50 NS |
| Standard Stückzahl | |
| Abmessungen Karton |
GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
Verfügbare Angebote
| Teilenummer | Menge | Datecode | |
|---|---|---|---|
| MT4LC1M16C3TG-5L | 1.000 | 2004+ | Anfrage senden |
FFFE (Form, Fit & Functional Equivalents)
| Teilenummer | Gehäuse | Spannungsversorgung | Geschwindigkeit | Betriebstemperatur |
|---|---|---|---|---|
| GM71V16160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71V18160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5S | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16R6TG-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| V53C318160AT50 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |