MT4LC1M16C3TG-5L
产品详情
| 脚位/封装 | TSOP2(44/50) |
| 外包装 | |
| 无铅/环保 | 含铅 |
| 电压(伏) | 3.3 V |
| 温度规格 | 0 C~+70 C |
| 速度 | 50 NS |
| 标准包装数量 | |
| 标准外箱 |
GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
供应链有货
| IC 编号 | 数量 | 生产年份 | |
|---|---|---|---|
| MT4LC1M16C3TG-5L | 1,000 | 2004+ | 索取报价 |
FFFE/互通料号 (形式，腳位和功能对等)
| IC 编号 | 脚位/封装 | 电压(伏) | 速度 | 温度规格 |
|---|---|---|---|---|
| GM71V16160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71V18160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5S | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16R6TG-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| V53C318160AT50 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |