MT4LC4M4E8TG-50

Produktübersicht

IC Picture

Bilder dienen nur der Illustration

Hersteller-Nummer MT4LC4M4E8TG-50
Hersteller MICRON
Produktkategorie DRAM
IC-Code 4MX4 EDO

Produktbeschreibung

Gehäuse TSOP2(24/26)
Verpackung
RoHS Leaded
Spannungsversorgung 3.3 V
Betriebstemperatur 0 C~+70 C
Geschwindigkeit 50 NS
Standard Stückzahl
Abmessungen Karton

GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address 4 Meg x 4 EDO DRAM D47.p65 – Rev.

Verfügbare Angebote

Teilenummer Menge Datecode
MT4LC4M4E8TG-50 6.000 05+ Anfrage senden

FFFE (Form, Fit & Functional Equivalents)

Teilenummer Gehäuse Spannungsversorgung Geschwindigkeit Betriebstemperatur
A42L2604V-50 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
GM71V17403CT-5 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
GM71V17403CT-50 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
GM71VS17403CLT-5 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
HY51V17404BT-50 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
HY51V17404CT-50 TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
IS41LV44002B-50CTG TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
IS41LV44002B-50CTG-TR TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
IS41LV44002B-50T TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C
IS41LV44002B-50T-TR TSOP2(24/26) 3.3 V 50 NS 0 C~+70 C