MT4LC4M4E8TG-50
产品详情
| 脚位/封装 | TSOP2(24/26) |
| 外包装 | |
| 无铅/环保 | 含铅 |
| 电压(伏) | 3.3 V |
| 温度规格 | 0 C~+70 C |
| 速度 | 50 NS |
| 标准包装数量 | |
| 标准外箱 |
GENERAL DESCRIPTION The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address 4 Meg x 4 EDO DRAM D47.p65 – Rev.
供应链有货
| IC 编号 | 数量 | 生产年份 | |
|---|---|---|---|
| MT4LC4M4E8TG-50 | 6,000 | 05+ | 索取报价 |
FFFE/互通料号 (形式，腳位和功能对等)
| IC 编号 | 脚位/封装 | 电压(伏) | 速度 | 温度规格 |
|---|---|---|---|---|
| A42L2604V-50 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71V17403CT-5 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71V17403CT-50 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71VS17403CLT-5 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| HY51V17404BT-50 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| HY51V17404CT-50 | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| IS41LV44002B-50CTG | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| IS41LV44002B-50CTG-TR | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| IS41LV44002B-50T | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |
| IS41LV44002B-50T-TR | TSOP2(24/26) | 3.3 V | 50 NS | 0 C~+70 C |