MT41J128M16JT-15E:D

Product Overview

IC Picture

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Manufacturer Part No MT41J128M16JT-15E:D
Brand MICRON
Item DDR3 SDRAM
Part No 128MX16 DDR3

Product Details

Package FBGA-96
Outpack
RoHS RoHS
Voltage 1.5 V
Temperature 0 C~+85 C
Speed 1333 MBPS
Std. Pack Qty
Std. Carton
Number Of Words 128M
Bit Organization x16
Density 2G
Max Clock Frequency 667 MHz
Production Status Production
Product Family DDR3 SDRAM
Version J
Die Revision D

Description DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode.

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
H5TQ2G63BFR-H9CR FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
H5TQ2G63DFR-H9C (128X16 DDR3- FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
H5TQ2G63DFR-H9C0 FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
H5TQ2G63DFR-H9CR FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
H5TQ2G63FFR-H9CR FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
HXB15H2G160CF-15H FBGA-96 1.5V 1333 MBPS 0 C~+85 C
IS43TR16128-15HBL FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
IS43TR16128A-15HBL FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
IS43TR16128B-15HB FBGA-96 1.5 V 1333 MBPS 0 C~+85 C
IS43TR16128B-15HBL FBGA-96 1.5 V 1333 MBPS 0 C~+85 C