MT46V32M16FN-5B:C

Product Overview

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Manufacturer Part No MT46V32M16FN-5B:C
Brand MICRON
Item DDR1 SDRAM
Part No 32MX16 DDR1
Alternate Names MT46V32M16FN5BC

Product Details

Package FBGA-60
Outpack
RoHS Leaded
Voltage 2.5 V
Temperature 0 C~+85 C
Speed 200 MHZ
Std. Pack Qty
Std. Carton
Number Of Words 32M
Bit Organization x16
Density 512M
Max Clock Frequency 200 MHz
Production Status Production
Product Family DDR SDRAM/Mobile LPDDR
Version F
Die Revision C

Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible.

Available Offers

Description Qty Datecode
MT46V32M16FN5BC 0 Get Quote
MT46V32M16FN-5B:C 1,238 08+ Get Quote
MT46V32M16FN-5B:C 4,000 09+ Get Quote
MT46V32M16FN5BC 512 Get Quote
MT46V32M16FN-5B:C 1,000 Get Quote
MT46V32M16FN5BC 704 Get Quote

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
IS43R16320D-5BL BGA-60 2.5 V 200 MHZ 0 C~+85 C
IS43R16320D-5BL-TR BGA-60 2.5 V 200 MHZ 0 C~+85 C
IS43R16320E-5BL BGA-60 2.5 V 200 MHZ 0 C~+85 C
IS43R16320E-5BL-TR BGA-60 2.5 V 200 MHZ 0 C~+85 C
IS43R16320F-5BL BGA-60 2.5 V 200 MHZ 0 C~+85 C
IS43R16320F-5BL-TR BGA-60 2.5 V 200 MHZ 0 C~+85 C
K4H511638B-GCCC FBGA-60 2.5 V 200 MHZ 0 C~+85 C
K4H511638B-GLCC FBGA-60 2.5 V 200 MHZ 0 C~+85 C
K4H511638B-ZCCC FBGA-60 2.5 V 200 MHZ 0 C~+85 C
K4H511638B-ZLCC FBGA-60 2.5 V 200 MHZ 0 C~+85 C