MT47H32M16HR-25RIT:G

Product Overview

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Manufacturer Part No MT47H32M16HR-25RIT:G
Brand MICRON
Item DDR2 SDRAM
Part No 32MX16 DDR2

Product Details

Package FBGA-84
Outpack
RoHS RoHS
Voltage 1.8 V
Temperature -40 C~+85 C
Speed 667 MBPS
Std. Pack Qty
Std. Carton
Number Of Words 32M
Bit Organization x16
Density 512M
Max Clock Frequency 400 MHz
Production Status Production
Product Family DDR2 SDRAM
Version H
Die Revision R

Description The DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS as well as to both edges of CK. Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read or a burst write of eight with another write. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR2 SDRAM enables concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18-compatible.

Available Offers

Description Qty Datecode
MT47H32M16HR-25RIT:G 1,000 1226 Get Quote

FFFE (Form, Fit & Functional Equivalents)

Description Package Voltage Speed Temperature
EM68B16CWQD-3IH FBGA-84 1.8 V 667 MBPS -40 C~+85 C
HY5PS121621CFP-Y4I FBGA-84 1.8 V 667 MBPS -40 C~+85 C
HY5PS121621CFP-Y5I FBGA-84 1.8 V 667 MBPS -40 C~+85 C
HY5PS121621CLFP-Y4I FBGA-84 1.8 V 667 MBPS -40 C~+85 C
HY5PS121621CLFP-Y5I FBGA-84 1.8 V 667 MBPS -40 C~+85 C
K4T51163QI-HIE60CV FBGA-84 1.8 V 667 MBPS -40 C~+85 C
K4T51163QJ-BIE6TCV FBGA-84 1.8 V 667 MBPS -40 C~+85 C
K4T51163QN-BIE6 FBGA-84 1.8 V 667 MBPS -40 C~+85 C
K4T51163QQ-BIE6 FBGA-84 1.8 V 667 MBPS -40 C~+85 C
K4T51163QQ-BIE6000 FBGA-84 1.8 V 667 MBPS -40 C~+85 C