| Package |
UBGA-144
|
| Outpack |
|
| RoHS |
RoHS
|
| Voltage |
1.8 V
|
| Temperature |
0 C~+85 C
|
| Speed |
533 MHZ
|
| Std. Pack Qty |
|
| Std. Carton |
|
| Number Of Words |
16M
|
| Bit Organization |
x36
|
| Density |
576M
|
| Max Clock Frequency |
400 MHz with (t)RC 20ns
|
| Production Status |
Production
|
| Product Family |
RLDRAM 1 & 2 Memory
|
| Version |
B
|
| Die Revision |
A
|
General Description
The Micron® reduced latency DRAM (RLDRAM®) II is a high-speed memory device
designed for high bandwidth data storage—telecommunications, networking, and
cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high
speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative edges
of the input data clock(s).
Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is
programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The µBGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.
