MT4C1M16C3TG-5
Product Details
| Package | TSOP2(44/50) |
| Outpack | |
| RoHS | Leaded |
| Voltage | 5.0 V |
| Temperature | 0 C~+70 C |
| Speed | 50 NS |
| Std. Pack Qty | |
| Std. Carton |
GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
Available Offers
| Description | Qty | Datecode | |
|---|---|---|---|
| MT4C1M16C3TG-5 | 3,000 | 9 | Get Quote |
| MT4C1M16C3TG-5 | 1,151 | 2001+ | Get Quote |
| MT4C1M16C3TG-5 | 4,000 | Get Quote | |
| MT4C1M16C3TG-5 | 3,000 | 2009+ | Get Quote |
| MT4C1M16C3TG-5 | 5,000 | 2004+ | Get Quote |
| MT4C1M16C3TG-5 | 25,880 | 2006+ | Get Quote |
| MT4C1M16C3TG-5 | 1,000 | 2001 | Get Quote |
| MT4C1M16C3TG-5 | 30,000 | 2008+ | Get Quote |
| MT4C1M16C3TG-5 | 24,000 | Get Quote | |
| MT4C1M16C3TG-5 | 6,000 | Get Quote |
FFFE (Form, Fit & Functional Equivalents)
| Description | Package | Voltage | Speed | Temperature |
|---|---|---|---|---|
| AS4C1M16F5-50TC | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C16160BT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C16160CT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C18160CT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| GM71C18160CT-50 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5116160LTT5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5118160LTT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| HM5118160TT-5 | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| MT4C1M16C3TG-5S | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |
| MT4C1M16C3TG-5T | TSOP2(44/50) | 5.0 V | 50 NS | 0 C~+70 C |