MT4LC1M16C3TG-5
Product Details
| Package | TSOP2(44/50) |
| Outpack | |
| RoHS | Leaded |
| Voltage | 3.3 V |
| Temperature | 0 C~+70 C |
| Speed | 50 NS |
| Std. Pack Qty | |
| Std. Carton |
GENERAL DESCRIPTION The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#.
Available Offers
| Description | Qty | Datecode | |
|---|---|---|---|
| MT4LC1M16C3TG-5 | 980 | 02+ | Get Quote |
| MT4LC1M16C3TG-5 | 20,000 | 10+ | Get Quote |
| MT4LC1M16C3TG-5 | 25,880 | 2006+ | Get Quote |
| MT4LC1M16C3TG-5 | 3,211 | 10+ | Get Quote |
| MT4LC1M16C3TG-5 | 30,000 | 2008+ | Get Quote |
| MT4LC1M16C3TG-5 | 1,000 | 2004+ | Get Quote |
| MT4LC1M16C3TG-5 | 11,000 | Get Quote | |
| MT4LC1M16C3TG-5 | 20,000 | 2004+ | Get Quote |
| MT4LC1M16C3TG-5 | 1,000 | 2002+ | Get Quote |
| MT4LC1M16C3TG-5 | 15,000 | 2004+ | Get Quote |
FFFE (Form, Fit & Functional Equivalents)
| Description | Package | Voltage | Speed | Temperature |
|---|---|---|---|---|
| GM71V16160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| GM71V18160CT-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5L | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16C3TG-5S | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| MT4LC1M16R6TG-5 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |
| V53C318160AT50 | TSOP2(44/50) | 3.3 V | 50 NS | 0 C~+70 C |