| Package |
TSOP
|
| Outpack |
|
| RoHS |
RoHS
|
| Voltage |
3.3 V
|
| Temperature |
0 C~+70 C
|
| Speed |
1 MHZ
|
| Std. Pack Qty |
|
| Std. Carton |
|
| Number Of Words |
4G
|
| Bit Organization |
x8
|
| Density |
32G
|
| Production Status |
Production
|
| Package Material |
Pb-free
|
| Interface |
Async only
|
| Level |
MLC-2
|
| Generation Feature Set |
2nd set of device features (rev only if different than 1st set)
|
| Speed Grade |
Async only
|
| Classification |
1-1-1-1 (Die-nCE-RnB-IO Channels)
|
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for
high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe
(DQS).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). For further details, see Device and Array Organization.
